1. Field of the Invention
The present invention relates to a semiconductor device.
2. Background of the Related Art
Heretofore, as a MOS (metal oxide semiconductor) type semiconductor device, an insulated gate field effect transistor (MOSFET: Metal Oxide Semiconductor Field Effect Transistor) is publicly known. A description will be given of a heretofore known MOS type semiconductor device with a planar gate MOSFET, wherein a MOS gate (an insulated gate formed of a metal oxide semiconductor) is provided on a semiconductor substrate in a planar shape, as an example. FIG. 7 illustrates plan views showing a configuration of a heretofore known planar gate MOSFET 500. FIG. 8 illustrates sectional views showing sectional structures along the section line X1-X1, section line X2-X2, and section line X3-X3 of FIG. 7B.
FIG. 7A shows a plan view layout of a source electrode 61, a gate pad electrode 62, and a gate runner 62a, which are disposed on the front surface of an n semiconductor substrate (a semiconductor chip) 51, and FIG. 7B shows in enlarged dimension the portion defined by the rectangular frame B of FIG. 7A. In FIG. 7B, a gate oxide film 55, a polysilicon gate electrode 56, and an interlayer insulating film 59, which are disposed on the front surface of the n semiconductor substrate 51, are omitted from the illustration, and contact holes 60, the source electrode 61, and the gate pad electrode 62 are shown by the dotted lines. FIG. 8A shows a sectional structure along the section line X1-X1 of FIG. 7B. FIG. 8B shows a sectional structure along the section line X2-X2 of FIG. 7B. FIG. 8C shows a sectional structure along the section line X3-X3 of FIG. 7B.
As shown in FIG. 7A, the planar gate MOSFET 500 includes the gate pad electrode 62 and source electrode 61 on the front surface of the n semiconductor substrate 51. The gate pad electrode 62 is disposed on the chip outer peripheral side of an active region. The source electrode 61 is disposed substantially all over the active region except in the portion in which the gate pad electrode 62 is disposed, and surrounds, for example, three sides of the substantially rectangular gate pad electrode 62. The gate runner 62a disposed so as to enclose the perimeter of the source electrode 61 is connected to the gate pad electrode 62. A breakdown voltage terminal structure portion is disposed in the outermost periphery (chip outermost periphery) of the planar gate MOSFET 500 so as to surround the perimeter of the active region. The active region is a region through which current flows when in on-state. The breakdown voltage terminal structure portion is a region which relaxes the substrate front surface side electric field of an n drift region 51a and maintains a breakdown voltage.
FIG. 8A shows a sectional structure along the section line X1-X1 which sections the gate pad electrode 62 in a direction (the lateral direction of the drawing) perpendicular to one side of the gate pad electrode 62 of FIG. 7B which is not opposed to the source electrode 61. As shown in FIG. 8A, one p well region 63 is formed in a surface layer of the front surface of the n semiconductor substrate 51 which forms the n drift region 51a, immediately below the gate pad electrode 62 (on the n drift region 51a side). One p high concentration region 64 is formed, in a surface layer on the front surface side, on the surface of the p well region 63. The polysilicon gate electrode 56 is disposed via the gate oxide film 55 on the front surface of the n semiconductor substrate 51. The interlayer insulating film 59 is formed on the surface of the polysilicon gate electrode 56, and furthermore, the gate pad electrode 62 is disposed on the surface of the interlayer insulating film 59.
The polysilicon gate electrode 56 is connected to the gate pad electrode 62 on the interlayer insulating film 59 by wires omitted from the illustration. An n drain region 57 is disposed in a surface layer of the rear surface of the n semiconductor substrate 51. Also, a drain electrode 58 connected to the n drain region 57 is disposed on the rear surface of the n semiconductor substrate 51. A portion of the n semiconductor substrate 51 is the n drift region 51a sandwiched between the p well region 63 and the n drain region 57. A pn junction 65a is formed at the interface between the p well region 63 and the n drift region 51a. A body diode 65 which is a parasitic diode is configured of the p high concentration region 64, p well region 63, n drift region 51a, and n drain region 57.
FIG. 8B shows a sectional structure along the section line X2-X2 which sections the portion of FIG. 7B between the gate pad electrode 62 and the source electrode 61 parallel to the section line X1-X1. The portion of FIG. 7B between the gate pad electrode 62 and the source electrode 61 is the portion sandwiched between the dotted line indicating the outer periphery of the gate pad electrode 62 and the dotted line indicating the outer periphery of the source electrode 61. As shown in FIG. 8B, a plurality of separate extension portions 52a are disposed in a surface layer of the n semiconductor substrate 51 immediately below the portion between the gate pad electrode 62 and the source electrode 61. Extension portions 54a are each selectively disposed, in a surface layer on the substrate front surface side, inside the extension portion 52a. The extension portions 52a are portions extending on the gate pad electrode 62 side of p channel regions 52, to be described hereafter, which are disposed immediately below the source electrode 61. The extension portions 54a are portions extending on the gate pad electrode 62 side of p contact regions 54, to be described hereafter, which are disposed immediately below the source electrode 61.
The polysilicon gate electrodes 56 are each disposed via the gate oxide film 55 so as to extend between adjacent extension portion 52a. The interlayer insulating film 59 is disposed on the surfaces of the polysilicon gate electrodes 56, and over surfaces of the extension portions 52a of the p channel regions 52, and of the extension portion 54a of the p contact regions 54, exposed between the polysilicon gate electrodes 56. The n drain region 57 and the drain electrode 58 are disposed on the rear surface side of the n semiconductor substrate 51, in the same way as immediately below the gate pad electrode 62. The pn junction 65a which is a parasitic diode is formed at the interface between the extension portion 52a of the p channel region 52 and the n drift region 51a. The body diode 65 is configured of the extension portions 54a of the p contact regions 54, the extension portions 52a of the p channel regions 52, the n drift region 51a, and the n drain region 57.
FIG. 8C shows a sectional structure along the section line X3-X3 which sections a portion on the chip outer peripheral side of the source electrode 61 of FIG. 7B parallel to the section line X1-X1. As shown in FIG. 8C, a plurality of the separate p channel regions 52 are disposed in a surface layer of the n semiconductor substrate 51, immediately below the source electrode 61. n source regions 53 and the p contact region 54 are selectively formed, in a surface layer on the substrate front surface side, inside each p channel region 52. The p contact regions 54 are each disposed on the central side of the p channel region 52 relative to the n source regions 53 so as to make contact with the n source regions 53. The polysilicon gate electrodes 56 are each disposed via the gate oxide film 55, on the surfaces of portions of adjacent p channel regions 52, each sandwiched between the n source region 53 and the n semiconductor substrate 51, so as to extend between the n source regions 53 disposed in the adjacent p channel regions 52.
The interlayer insulating film 59 is disposed on the surfaces of the polysilicon gate electrodes 56. The source electrode 61 is disposed on the surface of the interlayer insulating film 59. The contact holes 60 are formed in the interlayer insulating film 59, and the p contact regions 54 and the n source regions 53 are electrically connected to the source electrode 61 via the contact holes 60. The n drain region 57 and the drain electrode 58 are disposed on the rear surface side of the n semiconductor substrate 51, in the same way as immediately below the gate pad electrode 62. The pn junction 65a is formed at the interface between the p channel region 52 and the n drift region 51a. The body diode 65, which is a parasitic diode, is configured of the p contact regions 54, p channel regions 52, n drift region 51a, and n drain region 57.
As shown in FIG. 7B, the plurality of p channel regions 52 immediately below the source electrode 61 are disposed in a plan view layout of stripes. Two n source regions 53 which are, for example, in straight lines are separately disposed, parallel to a direction in which the p channel regions 52 extend in stripes, inside each p channel region 52. The p contact regions 54 are each disposed between the separately disposed n source regions 53 so as to make contact with the respective n source regions 53. The p channel regions 52 and the p contact regions 54 are linked to the p well region 63 and p high concentration region 64 immediately below the gate pad electrode 62, via extension portions 52a and 54a, respectively.
The p channel regions 52, the extension portions 52a of the p channel regions 52, and the p well region 63 are formed by ion implantation using the same mask at the same impurity concentration and to the same diffusion depth. Also, the p contact regions 54, the extension portions 54a of the p contact regions 54, and the p high concentration region 64 are formed by ion implantation using the same mask at the same impurity concentration and to the same diffusion depth.
In this way, the one p well region 63 formed immediately below the gate pad electrode 62 is linked to the plurality of p channel regions 52 on the underside of the source electrode 61. By so doing, when a positive voltage is applied between the drain and source of the planar gate MOSFET 500, a depletion layer spreading from the pn junction 65a between the p channel regions 52 and p well region 63 and the n drift region 51a spreads uniformly immediately below the gate pad electrode 62. Therefore, it is possible to suppress an electric field concentration immediately below the gate pad electrode 62, and thus secure a high breakdown voltage.
A description will be given of a reverse recovery operation (a motion of excessive holes 67 and electrons 68 in a reverse recovery process) of the body diode 65 of the planar gate MOSFET 500. FIG. 9 illustrates explanatory diagrams showing a reverse recovery operation of the body diode 65 of the planar gate MOSFET 500 of FIG. 8. FIGS. 9A and 9B show a case in which a forward current If flows through the body diode 65, and FIGS. 9C and 9D show a case in which a reverse current Ir flows through the body diode 65. Also, FIGS. 9A and 9C show a motion of carriers immediately below the gate pad electrode 62, and FIGS. 9B and 9D show a motion of carriers immediately below the source electrode 61.
The body diode 65, which is a parasitic diode, is configured of the p high concentration region 64, p well region 63, n drift region 51a, and n drift region 57, as heretofore described, immediately below the gate pad electrode 62 shown in FIGS. 9A and 9C. The body diode 65 which is a parasitic diode is configured of the p contact regions 54, p channel regions 52, n drift region 51a, and n drain region 57, as heretofore described, immediately below the source electrode 61 shown in FIGS. 9B and 9D.
As shown in FIGS. 9A and 9B, when a negative voltage is applied between the drain and source of the planar gate MOSFET 500, the forward current If flows through the body diode 65. Excess holes 67 and excess electrons 68 are stored in the n drift region 51a due to the forward current If. Meanwhile, as shown in FIGS. 9C and 9D, when the body diode 65 makes a transition to the reverse recovery process, the excess holes 67 flow into the p channel regions 52 and p well region 63, and the excess electrons 68 flow into the n drain region 57, as the reverse current Ir. As a result of this, the condition in which carriers are excessively stored is eliminated, and the breakdown voltage of the planar gate MOSFET 500 is maintained.
In this way, when the reverse current Ir flows through the body diode 65, the reverse current Ir also flows into the p well region 63 and p high concentration region 64 immediately below the gate pad electrode 62. Also, the reverse current Ir having flowed into the p well region 63 and p high concentration region 64 flows from the p well region 63 and p high concentration region 64 into the p channel regions 52 and p contact regions 54, and furthermore, flows into the source electrode 61 by way of the contact holes 60. The potential of a portion of the p well region 63 immediately below the center of the gate pad electrode 62 rises due to resistance Rp (refer to FIG. 7B) in the current path of the reverse current Ir.
The potential of the portion of the p well region 63 immediately below the center of the gate pad electrode 62 rises due to the reverse current Ir flowing through the body diode 65 in this way, but the p well region 63 is formed as one region all over immediately below the gate pad electrode 62. Therefore, the surface area of the pn junction 65a of the body diode 65 formed immediately below the gate pad electrode 62 is wide, and the resistance Rp of the current path through which the excess holes 67 flow from the p contact regions 54 into the source electrode 61 is small. Consequently, a rise in the potential of the portion of the p well region 63 immediately below the center of the gate pad electrode 62 is small.
However, as the p well region 63 and the p high concentration region 64 are disposed as one region all over immediately below the gate pad electrode 62, a portion partly low in resistance occurs when the impurity concentration of the p well region 63 and p high concentration region 64 varies in their respective planes. Current (the holes 67) flows into the portion low in resistance from around, and flows into the p channel regions 52 linked to the portion low in resistance. Therefore, there is fear that the potential of the p well region 63 and p high concentration region 64 rises, and that a large voltage is applied to the gate oxide film 55 sandwiched between the p well region 63 and the polysilicon gate electrode 56, thus causing breakdown of the gate oxide film 55.
When using the planar gate MOSFET 500 as a switch, the body diode 65 functions as a free wheeling diode (FWD). FIG. 10 is an explanatory diagram showing an operation of an inverter circuit to which an inductive load M is connected. FIG. 10 shows a reflux current Io flowing through the inverter circuit in an operation of the inverter circuit. A description will be given, as an example, of a three-phase output inverter circuit wherein half bridge circuits, each having switches M1 and M2 connected in series, are connected in parallel between terminals P and N. As the switches M1 and M2, for example, the heretofore described planar gate MOSFETs 500 are used. An inductive load M is connected between the switches M1 and M2 of the half bridge circuits. The free wheeling diode FWD is connected in parallel to each switch M1 and M2.
As shown in FIG. 10, when the switch M1 is turned on in a condition in which the reflux current Io is flowing through the inductive load M and free wheeling diode FWD, the switch M1 is turned on, and a current IM1 flows from the switch M1 toward the switch M2. The current IM1 flows so as to cancel out the reflux current Io which is already flowing through the free wheeling diode FWD and body diode 65, thus bringing the free wheeling diode FWD and body diode 65 into off-state. In FIG. 10, the switch M1 is an upper arm MOSFET, the switch M2 is a lower arm MOSFET, the current IM1 is the current of the switch M1, the terminal P is the positive terminal of the inverter circuit, and the terminal N is the negative terminal of the inverter circuit. The forward current If shown in FIG. 9A is one portion of the reflux current Io flowing through the inductive load M and free wheeling diode FWD in an operation of the inverter circuit to which the inductive load M is connected, and is the forward current If flowing through the body diode 65.
Next, a description will be given, as another example of the heretofore known MOS semiconductor device, of a MOSFET of a super junction (SJ) structure (hereafter referred to as a super junction MOSFET) with a drift layer as a parallel pn layer wherein n-type regions and p-type regions, which are made higher in impurity concentration, are alternately disposed. FIG. 11 illustrates plan views showing a configuration of a heretofore known super junction MOSFET 600. FIG. 12 illustrates sectional views showing sectional structures along the section line X1-X-1, section line X2-X2, and section line X3-X3 of FIG. 11B. FIG. 11A shows a plan view layout of a source electrode 84, a gate pad electrode 85, and a gate runner 85a, which are disposed on the front surface of a semiconductor substrate (hereafter referred to as a super junction semiconductor substrate (a semiconductor chip)) 71, and shows, by the dotted lines, parallel pn layers (pn parallel columns) 74 wherein n-type columns (n columns) and p-type columns (p columns) are alternately disposed. FIG. 11B shows in enlarged dimension the portion defined by the rectangular frame B of FIG. 11A. In FIG. 11B, gate oxide films 77, polysilicon gate electrodes 78, and an interlayer insulating film 82, which are disposed on the front surface of the super junction semiconductor substrate 71, are omitted from the illustration, and contact holes 83, the source electrode 84, and the gate pad electrode 85 are shown by the dotted lines.
FIG. 12(a) shows a sectional structure along the section line X1-X1 of FIG. 11B. FIG. 12(b) shows a sectional structure along the section line X2-X2 of FIG. 11B. FIG. 12(c) shows a sectional structure along the section line X3-X3 of FIG. 11B. As shown in FIG. 11A, the super junction MOSFET 600 includes the gate pad electrode 85 and source electrode 84 on the front surface of the super junction semiconductor substrate 71. The gate runner 85a disposed so as to enclose the perimeter of the source electrode 84 is connected to the gate pad electrode 85. The plan view layout of the gate pad electrode 85, source electrode 84, gate runner 85a, and breakdown voltage terminal structure portion is the same as that of the gate pad electrode 62, source electrode 61, gate runner 62a, and breakdown voltage terminal portion of the planar gate MOSFET 500 shown in FIG. 7A.
FIG. 12(a) shows a sectional structure along the section line X1-X1 which sections the gate pad electrode 85 in a direction (the lateral direction of the drawing) perpendicular to one side of the gate pad electrode 85 of FIG. 11B which is not opposed to the source electrode 84. As shown in FIG. 12(a), the pn parallel columns 74 wherein p columns 72 and n columns 73 are alternately disposed are disposed on a first n layer 71 (on a surface opposite to the side of an n drain region 80 to be described hereafter), immediately below the gate pad electrode 85 (on the pn column 74 side). A second n layer 71b is disposed on the pn parallel columns 74. p well regions 86 which pass through the second n layer 71b and reach the p columns 72 of the pn parallel columns 74 are disposed in positions inside the second n layer 71b opposite in a depth direction to the respective p columns 72 of the pn parallel columns 74. The p well regions 86 have the function of maintaining the breakdown voltage immediately below the gate pad electrode 85.
The p high concentration regions 87 are each selectively disposed, in a surface layer on the substrate front surface side, inside the p well region 86. The polysilicon gate electrodes 78 are each disposed via the gate oxide film 77 so as to extend between adjacent p well regions 86. The interlayer insulating film 82 is disposed on the surfaces of the polysilicon gate electrodes 78, and over surfaces of the p well regions 86 and p high concentration regions 87, each exposed between the polysilicon gate electrodes 78. The gate pad electrode 85 is disposed on the surface of the interlayer insulating film 82. The polysilicon gate electrodes 78 are electrically connected to the gate pad electrode 85 by wires omitted from the illustration. The n drain region 80 is disposed on a surface of the first n layer 71a opposite to the pn parallel column 74 side. The super junction semiconductor substrate 71 is formed by stacking the n drain region 80, first n layer 71a, pn parallel columns 74, and second n layer 71b in order from the drain side. A drain electrode 81 is disposed connected to the n drain region 80.
A pn junction 93 is formed at the interface (the portion shown by the solid line) between the p region of the p well region 86 and p column 72 and the n region of the second n layer 71b, n column 73, and first n layer 71a. A body diode 91 is configured of the p high concentration regions 87, p well regions 86, p columns 72, first n layer 71a, and n drain region 80.
FIG. 12(b) shows a sectional view along the section line X2-X2 which sections the portion between the gate pad electrode 85 and source electrode 84 of FIG. 11B parallel to the section line X1-X1. The portion between the gate pad electrode 85 and source electrode 84 of FIG. 11B is the portion sandwiched between the dotted line indicating the outer periphery of the gate pad electrode 85 and the dotted line indicating the outer periphery of the source electrode 84. As shown in FIG. 12(b), the pn parallel columns 74 and the second n layer 71b are disposed in order on the first n layer 71a, immediately below the portion between the gate pad electrode 85 and the source electrode 84, in the same way as immediately below the gate pad electrode 85. Extension portions 75a, which pass through the second n layer 71b and reach the p columns 72 of the pn parallel columns 74, are disposed in positions inside the second n layer 71b opposite in the depth direction to the respective p columns 72 of the pn parallel columns 74.
Extension portions 79a are each selectively disposed, in a surface layer on the substrate front surface side, inside the extension portion 75a. The extension portions 75a are portions, extending on the gate pad electrode 85 side, of p channel regions 75, to be described hereafter, which are disposed immediately below the source electrode 84. The extension portions 79a are portions, extending on the gate pad electrode 85 side, of p contact regions 79, to be described hereafter, which are disposed immediately below the source electrode 84. The polysilicon gate electrodes 78 are each disposed via the gate oxide film 77 so as to extend between adjacent extension portions 75a. The interlayer insulating film 82 is disposed on the surfaces of the polysilicon gate electrodes 78, and over surfaces of the extension portions 75a of the p channel regions 75 and the extension portions 79a of the p contact regions 79, each exposed between the polysilicon gate electrodes 78. The n drain region 80 and the drain electrode 81 are disposed on the side of the first n layer 71a opposite to the pn parallel column 74 side, in the same way as immediately below the gate pad electrode 85.
A pn junction 93 is formed at the interface (the portion shown by the thick line) between the p region of the extension portion 75a of the p channel region 75 and the p column 72 and the n region of the second n layer 71b, n column 73, and first n layer 71a. The body diode 91 is configured of the extension portions 79a of the p contact regions 79, the extension portions 75a of the p channel regions 75, the p columns 72, the first n layer 71a, and the n drain region 80.
FIG. 12(c) shows a sectional structure along the section line X3-X3 which sections a portion on the chip outer peripheral side of the source electrode 84 of FIG. 11B parallel to the section line X1-X1. As shown in FIG. 12(c), the pn parallel columns 74 and the second n layer 71b are disposed in order on the first n layer 71a, immediately below the source electrode 84, in the same way as immediately below the gate pad electrode 85. The p channel regions 75, which pass through the second n layer 71b and reach the p columns 72 of the pn parallel columns 74, are disposed in positions inside the second n layer 71b opposite in the depth direction to the respective p columns 72 of the pn parallel columns 74. The n source regions 76 and the p contact region 79 are selectively formed, in a surface layer on the substrate front surface side, inside each p channel region 75. The p contact regions 79 are each disposed on the central side of the p channel region 75 relative to the n source regions 76 so as to make contact with the n source regions 76.
The polysilicon gate electrodes 78 are each disposed via the gate oxide film 77, on the surfaces of portions of adjacent p channel regions 75, each sandwiched between the n source region 76 and the second n layer 71b, so as to extend between the n source regions 76 disposed in the adjacent p channel regions 75. The interlayer insulating film 82 is disposed on the surfaces of the polysilicon gate electrodes 78. The source electrode 84 is disposed on the surface of the interlayer insulating film 82. The contact holes 83 are formed in the interlayer insulating film 82, and the p contact regions 79 and the n source regions 76 are electrically connected to the source electrode 84 via the contact holes 83. The n drain region 80 and the drain electrode 81 are disposed on the side of the first n layer 71a opposite to the pn parallel column 74 side, in the same way as immediately below the gate pad electrode 85.
A pn junction 92 is formed at the interface (the portion shown by the thick line) between the p region of the p channel region 75 and p column 72 and the n region of the second n layer 71b, n column 73, and first n layer 71a. The body diode 91 is configured of the p contact regions 79, p channel regions 75, p columns 72, first n layer 71a, and n drain region 80.
The pn parallel column 74 disposed immediately below the gate pad electrode 85, the pn parallel column 74 disposed immediately below the portion between the gate pad electrode 85 and the source electrode 84, and the pn parallel column 74 disposed immediately below the source electrode 84 are integrally formed. The pn parallel columns 74, having a plan view shape of stripes, are the same in impurity concentration, shape, and dimension, and are formed at the same time. That is, the pn parallel columns 74 are disposed in a plan view layout of stripes wherein the p column 72 and the n column 73 are alternately disposed, as shown in FIG. 11A.
Also, as shown in FIG. 11B, the plan view layout of the p channel regions 75, n source regions 76, and p contact regions 79 is the same as that of the p channel regions 52, n source regions 53, and p contact regions 54 of the planar gate MOSFET 500 shown in FIG. 7B. The p well regions 86 immediately below the gate pad electrode 85 and the p channel regions 75 immediately below the source electrode 84 are linked to each other via the extension portions 75a of the p channel regions 75. The p well regions 86, being disposed in a plan view layout of stripes parallel to the p channel regions 75, are the same in impurity concentration, shape, and dimension, and are formed at the same time as the p channel regions 75. Also, the p high concentration regions 87 immediately below the gate pad electrode 85 and the p contact regions 79 immediately below the source electrode 84 are linked to each other via the extension portions 79a of the p contact regions 79. The p high concentration regions 87, being disposed in a plan view layout of stripes parallel to the p contact regions 79, are the same in impurity concentration, shape, and dimension, and are formed at the same time as the p contact regions 79.
In this way, in the super junction MOSFET 600, in order to achieve the uniformity in the in-plane breakdown voltage of the chip, the pn parallel columns 74 are also formed immediately below the gate pad electrode 85 in the same way as immediately below the source electrode 84. The p well regions 86, immediately below the gate pad electrode 85, to be linked to the p channel regions 75 immediately below the source electrode 84, although having a shape different from the p channel regions 75, hardly affect the in-plane breakdown voltage of the chip.
Also, the super junction MOSFET 600 is different from the planar gate MOSFET 500 shown in FIG. 7 in that the p well regions 86 and the p high concentration regions 87 are disposed in a plan view layout of stripes, rather than disposing one p region all over immediately below the gate pad electrode 85. Therefore, the p well regions 86 and p high concentration regions 87 of straight lines configuring the stripes are smaller in surface area, respectively, than the p well regions 63 and p high concentration regions 64 immediately below the gate pad electrode 62 of the planar gate MOSFET 500 of FIG. 7. Consequently, a rise in the potential of the p well regions 86 and p high concentration regions 87 is suppressed even though the p well regions 86 and the p high concentration regions 87 vary in impurity concentration, thus forming a portion partly low in resistance, and current (the holes 67 acting as the reverse current Ir to be described hereafter) flows into the portion low in resistance from around. Therefore, a voltage applied to the gate oxide film 77 sandwiched between the p well region 86 and the polysilicon gate electrode 78 is small, and breakdown of the gate oxide film 77 due to the variation in impurity concentration is suppressed.
Also, in the super junction MOSFET 600, the area of the pn junction 92 (body diode 91) immediately below the gate pad electrode 85 is large compared with the area of the pn junction 65a (body diode 65) immediately below the gate pad electrode 62 of the planar gate MOSFET 500. Therefore, in a reverse recovery process of the body diode 91, the amount of holes 67 flowing into the p channel regions 75 and p contact regions 79 by way of the p well regions 86 and p high concentration regions 87 immediately below the gate pad electrode 85 is large compared with in the planar gate MOSFET 500. However, the holes 67 flow, comparatively evenly dispersed, through the p well regions 86 and p high concentration regions 87, and do not flow concentrated in a specific p well region 86 or p high concentration region 87 which is low in resistance.
However, as the p well regions 86 and p high concentration regions 87 of the super junction MOSFET 600 are disposed in stripes, the resistance R of the current path of current (the holes 67) is large (refer to FIG. 11B). Therefore, there is fear that a rise in the potential of a portion of the p well region 86 of the super junction MOSFET 600 immediately below the center of the gate pad electrode 85 increases, thus causing breakdown of the gate oxide film 77.
A description will be given of a motion of the holes 67 in the reverse recovery process of the body diode 91 of the super junction MOSFET 600. FIG. 13 illustrates explanatory diagrams showing a reverse recovery operation of the body diode 91 of the super junction MOSFET 600 of FIG. 12. FIGS. 13A and 13B show a case in which the forward current If flows through the body diode 91, and FIGS. 13C and 13D show a case in which the reverse current Ir flows through the body diode 91. Also, FIGS. 13A and 13C show a motion of carriers immediately below the gate pad electrode 85, and FIGS. 13B and 13D show a motion of carriers immediately below the source electrode 84.
As shown in FIGS. 13A and 13B, when the body diode 91 of the super junction MOSFET 600 is forward biased, and the forward current If flows through the body diode 91, excess holes 67 and electrons 68 are stored in the p columns 72 and n columns 73. Meanwhile, as shown in FIGS. 13C and 13D, when the body diode 91 makes a transition to the reverse recovery process, the excess holes 67 flow into the p well regions 86 and p channel regions 75, and the excess electrons 68 flow into the n drain region 80, as the reverse current Ir. The holes 67 flowing through the p well regions 86 and p high concentration regions 87 flow into the source electrode 84 by way of the p channel regions 75 and p contact regions 79, and the holes 67 having flowed into the p channel regions 75 flow into the source electrode 84 by way of the contact holes 83.
JP-A-2012-164879 (PTL 1) discloses a device having an element region, a conductive region, and an outer peripheral region, which form a trench structure MOSFET, wherein an outer peripheral end of the element region has outwardly angled corners in the vicinity of the conductive region, thereby improving breakdown withstand when in reverse recovery while securing an element breakdown voltage.
Japanese Patent No. 4,962,665 (PTL 2) discloses a device wherein p contact regions to which p-type impurities are added at a high concentration are provided on the surfaces of p well regions immediately below a gate pad electrode, thereby preventing breakdown of a gate insulating film.
Japanese Patent No. 4,962,664 (PTL 3) discloses a device wherein the p-type impurity concentration of a surface layer portion is increased by additional ion implantation to enhance the conductivity of p well regions below a gate pad electrode, thereby preventing breakdown of a gate insulating film.
JP-A-5-343692 (PTL 4) discloses a device wherein trenches are formed in portions, immediately below a source electrode, of p well regions provided from immediately below a gate pad electrode to immediately below the source electrode, and are filled with a tungsten layer, and the tungsten layer and the source electrode are connected, thereby preventing breakdown of a gate insulating film.
That is, in PTLs 2 to 4, the p well regions disposed immediately below the gate pad electrode are electrically connected to an end portion of the source electrode disposed around the gate pad electrode, and excess holes having flowed into the p well regions when a body diode is reversely recovered are extracted, thereby preventing breakdown of the gate insulating film immediately below the gate pad electrode.
In the reverse recovery process of the body diode 91 of the super junction MOSFET 600 shown in FIG. 13, a voltage of a size computed by the product of a current (the holes 67) flowing through the p well regions 86 immediately below the gate pad electrode 85 and the resistance of the current path, through which the current flows, is generated. When the potential of the source electrode 84 is made a reference, the voltage generated in the reverse recovery process of the body diode 91 is highest in the portion of the p well region 86 immediately below the center of the gate pad electrode 85. Also, the voltage generated in the reverse recovery process of the body diode 91 is applied to the gate oxide film 77 on the surface of the portion sandwiched between adjacent p well regions 86 disposed immediately below the gate pad electrode 85, and to the polysilicon gate electrode 78 disposed on the gate oxide film 77. Furthermore, as a negative gate voltage (for example, on the order of −10V) applied to the polysilicon gate electrode 78 is added, in addition to the voltage generated in the reverse recovery process of the body diode 91, a high voltage is applied to the gate oxide film 77.
In this way, when the electric field inside the gate oxide film 77 exceeds the breakdown strength of the gate oxide film 77 by a high voltage being applied to the gate oxide film 77, the gate oxide film 77 suffers breakdown. FIG. 14 illustrates explanatory diagrams showing a breakdown portion of the gate oxide film 77 when the body diode 91 of the heretofore known super junction MOSFET 600 of FIG. 13 is reversely recovered. As the voltage generated in the reverse recovery process of the body diode 91 is highest in the portion of the p well region 86 immediately below the center of the gate pad electrode 85, as heretofore described, the breakdown portion of the gate oxide film 77 is the portion immediately below the center of the gate pad electrode 85, as shown in FIG. 14. When the gate oxide film 77 suffers breakdown, the polysilicon gate electrode 78 and the p well region 86 are short-circuited, the gate and source of the super junction MOSFET 600 comes into a short circuit condition, meaning that the super junction MOSFET 600 fails to operate properly.
In order to solve the heretofore described problems of the heretofore known technologies, the invention has for its object to provide a semiconductor device which can prevent breakdown of the gate insulating film occurring in the reverse recovery process of the body diode.